As the level of integration increases in an LSI chip, the reduction in a package size is also in strong demand, and various mount package structures are proposed. In recent years, developments have been vigorously conducted in attempts to form and laminate a through electrode on a semiconductor bare chip. At the same time, a double-sided electrode package in real size is likely to be available in the market in the future. No matter whichever technology is employed, the conventional double-sided electrode package is always in need of a through electrode structure, whereas the application of the existing method of insulating a through hole to the mounting process of the semiconductor has been difficult due to high temperature processing. Hence, the formation of through holes on the semiconductor substrate and its insulating method are still fraught with problems, and it is desired to wire without necessitating the through holes.
In the meantime, in recent years, nano metal particles have been developed. The materials include copper, silver, gold, and the like. These fine particles have a great feature in that a direct drawing can be made by the ink jet system. Organic solvent contains the nano metal particles, and by using these particles, a desired pattern is drawn by the ink jet method which is put into a practice by a printer. Noble metals such as silver and gold are by nature hard to be oxidized, whereas copper has a nature easily oxidized comparing with silver and gold. After a wiring pattern drawing, a thermal treatment (to the extent of 200 to 300° C.) is required, in which the organic solvent is vaporized, and further, copper particles are mutually adhered. However, even during the thermal treatment, the surface of copper ends up being oxidized. In the nano metal particles, there is a problem that a ratio of atom of the surface portion is large, and as a result, a wiring resistance becomes high due to the formation of surface oxidized copper.
Further, the thermal treatment alone is unable to sufficiently remove the organic solvent, and this brings about circumstances where it is not possible to reduce electric resistivity of the copper wiring nor is it possible to use the copper wiring as a wiring. With respect to the lowering of an electric resistance after the drawing, there is still no sufficient solution found particularly in the case of copper.
In the technology in which not a direct drawing system such as the ink jet system but lithography mixed with resist is used, a lowering of the resistance of copper has been proposed in various manners, and, for example, Patent Document 1 is known in this respect. Restoration thermal treatment technology used here is performed at the temperatures of 200 to 450° C. in an inert gas (or in vacuum) containing molecular (H2) hydrogen below 4%. Thus, this technology, while using copper fine particles, is not a direct drawing system, and the reduction temperature thereof is high such as 200 to 450° C. When the temperature is high as much as that, it is difficult to use this technology in the mounting area of the semiconductor. Patent Document 1: Japanese Patent Laid-Open No. 2002-75999.
An object of the present invention is to solve such a problem as described above so as to easily manufacture and provide a double sided electrode package without requiring the through electrode technology. As a result, a wafer level type double sided electrode package, a lead frame type double-sided electrode package or an organic substrate type double-sided electrode package (BGA type) can be manufactured, and apart from the application to the conventional mobile phone, can be effectively used as a package for each type of sensors (such as sound, magnetic, and pressure).
Further, the present invention forms a side wiring by the ink jet system using the nano metal particles. Particularly, when copper is used, a problem such as a wiring resistance becoming high by the formation of surface oxidation copper is solved, thereby attempting to lower the resistance after the drawing and enabling the side wiring to be mountable on the semiconductor.